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NAND memory adress for BSP RRS feed

  • Question

  • Hi. I have 2 boards with one different - boards have different NAND flash chip.

    I run conpiled image in first board - all work. then I try install this image into second board. and it didn't install.

    I think problem - different NAND flash and I must change BSP for second device and write correct boot addrsses for second device and his NAND flash.

    Can anybody tell me where I can change boot address for NAND flash in BSP. and how can I know this new addresses.

    Thanks and hope for you reply.

    Tuesday, July 10, 2012 11:28 AM

All replies

  • If what changes from one board to the other is only the NAND flash chip, the  hardware connection between the CPU and the flash has not changed so the physical address has not changed: one problem can be different timing requirements for accessing the new flash with respect to the old one. In this case you need to modify the static memory controller settings: how to do it depends on the CPU you're using

    Anyway: The physical address is defined by the hardware connection between the CPU and the NAND flash. Once you have it you need to modify the entry in the OEMAddressTable which maps the physical address of the NAND to a virtual address.

    If you search your BSP code for OEMAddressTable you may find some comments which directs you to the right entry to change.



    Luca Calligaris lucaDOTcalligarisATeurotechDOTcom www.eurotech.com Check my blog: http://lcalligaris.wordpress.com

    Tuesday, July 10, 2012 12:33 PM
  • and what to do if  hardware connection between the CPU and the flash has changed?
    Tuesday, July 10, 2012 1:13 PM
  • I answered in the 2nd paragraph, you have to understand which physical address is related to the NAND: suppose that your CPU memory controller has different chip select lines (CS0, CS1, CS2, ...) which corresponds to physical addresses 0x20000000, 0x40000000, 0x60000000, ... depending to which CS the NAND is connected to you have to set the appropriate physical address in the OEMAddressTable memory map

    Luca Calligaris lucaDOTcalligarisATeurotechDOTcom www.eurotech.com Check my blog: http://lcalligaris.wordpress.com

    Tuesday, July 10, 2012 3:48 PM
  • Thanks,

    but I cant found OEMAddressTable. What file I must search?

    Wednesday, July 11, 2012 6:00 AM
  • It depends on BSP. I'm working on iMX31 Windows CE 6.0 R3 BSP and OEMAddressTable is inside the file oemaddrtab_cfg.inc at the following path :

    C:\<WINCEROOT>\PLATFORM\<BSP>\SRC\INC --> tipically this is the right path where searching for

    Inside is declared a global exported variable g_oalAddressTable that defines the OEMAddressTable.


    Wednesday, July 11, 2012 6:22 AM
  • I found 2 file

    ..\BSP_Folder\cesysgen\files\config.bib

    ..\BSP_Folder\Files\config.bib

    both contain next

    ;
    ; Copyright (c) Microsoft Corporation.  All rights reserved.
    ;
    ;
    ; Use of this source code is subject to the terms of the Microsoft end-user
    ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
    ; If you did not accept the terms of the EULA, you are not authorized to use
    ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
    ; install media.
    ;
    ;------------------------------------------------------------------------------
    ; 
    ; Copyright (C) 2007-2009, Freescale Semiconductor, Inc. All Rights Reserved.
    ; THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
    ; AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT 
    ; 
    ;------------------------------------------------------------------------------
    ;
    ; Memory Map
    ; ----------
    ;
    ; 8000.0000 -+
    ;            | Bootloader Stack (64KB)
    ; 8001.0000 -+
    ;            | Bootloader RAM (256KB)
    ; 8005.0000 -+
    ;            | Bootloader Code (256KB)
    ; 8009.0000 -+
    ;            | GAP (reserved for future)
    ; 800F.7000 -+
    ;            | ARGS (4KB)
    ; 800F.8000 -+
    ;            | USB KITL transfers (32 KB)
    ; 8010.0000  |
    ;            | Display Frame buffer ( 1 MB)
    ; 8020.0000  |
    ;            |
    ;            | OS (NK) Code (32MB)
    ;            |
    ; 8220.0000 -+   **auto-size**
    ;            |
    ;            | OS (NK) RAM  (30MB)
    ;            |
    ; 8400.0000 -+
    ;
    ;******************************************************************************
    
    
    ;**************************** MEMORY SECTION ***************************
    MEMORY
    
    ; ----------------- Reserved Region Mapping (2 MB) ---------------------
    ;   Start Addr      End Addr        Mem Type    Region Name     Size
    ;    80000000       80010000        SDRAM       STACK           64KB
    ;    80010000       80050000        SDRAM       RAM             256KB
    ;    80050000       80090000        SDRAM       EBOOT           256KB
    ;    80090000       800F7000        SDRAM       RSVD            412KB
    ;    800F7000       800F8000        SDRAM       ARGS            4KB
    ;    800F8000       80100000        SDRAM       USB             32KB  
    ;    80100000       80200000        SDRAM       DISPLAY         1MB
    ; ----------------------------------------------------------------------
    ;                   Name        Address     Size        Type
                        RSVD        80000000    000F7000    RESERVED     ;0x8000_0000 -> 0x8010_0000  (1MB EBOOT RAM & ARGS)
                        ARGS        800F7000    00001000    RESERVED
                        USB         800F8000    00008000    RESERVED
                        DISPLAY     80100000    00100000    RESERVED
    
    IF IMGFLASH !
        #define NK_START    80200000
        IF IMGUUT
            #define NK_SIZE     00300000    ;3MB
        ENDIF
        
        IF IMGUUT !
            #define NK_SIZE     02000000    ;32MB
        ENDIF    
        #define RAM_START   82200000
        #define RAM_SIZE    01E00000    ;30MB    
    ENDIF
    
    IF IMGFLASH
        IF IMGEBOOT
            #define NK_START    90040000
            #define NK_SIZE     03FC0000
            #define RAM_START   80200000
            #define RAM_SIZE    07500000
        ENDIF
    
        IF IMGEBOOT !
            #define NK_START    90000000
            #define NK_SIZE     020C0000
            #define RAM_START   88100000
            #define RAM_SIZE     07500000
        ENDIF
    ENDIF
    
    ; ----------------------------------------------------------------------
    ;                   Name        Address      Size        Type
                        NK          $(NK_START)  $(NK_SIZE)  RAMIMAGE
                        RAM         $(RAM_START) $(RAM_SIZE) RAM
                        OCRAM       88000000     00008000    RESERVED
    
    ; This fix-up variable is a bitfield that can be used to initialize 
    ; the Kernel debug zones per kernel.h. Uncomment the line and 
    ; change the hexadecimal bits to enable the desired zones. The 
    ; default value (0x00000100) enables the ZONE_DEBUG. 
    ; 
    ;kernel.dll:initialKernelLogZones 00000000 00000100 FIXUPVAR 
    ;kernel.dll:initialKernelLogZones 00000000 7FFFFFFF FIXUPVAR 
    
    ;
    ; This fix-up variable is a bitfield that can be used to initialize
    ; the OAL debug zones per oal_log.h.  Uncomment the line and
    ; change the hexidecimal bits to enable the desired zones.  The
    ; default value (0x0000000B) enables the OAL_LOG_ERROR,
    ; OAL_LOG_WARN, and OAL_LOG_INFO zones, and will be used by
    ; OEMInit if the line remains commented out.
    ;
    ;  nk.exe:initialOALLogZones        00000000 0x0000000B       FIXUPVAR
    ;
    
    ; This fix-up variable determines the amount of memory the BSP reserves
    ; for Watson dump capture (see also the OEMInit() function in the OAL).
    ; The current default behavior is to default to zero unless the image has
    ; SYSGEN_WATSON_DMPGEN defined, then the default size is 300KB (0x4B000).
    ;
    ; If WATSONBUFFERSIZE is defined, use its value.  Otherwise use 300KB.
    ;
    ; @CESYSGEN IF CE_MODULES_OSAXST0
    ; @CESYSGEN ENDIF CE_MODULES_OSAXST0
    
    ;**************************** CONFIG SECTION ***************************
    CONFIG
    
    ; ---------------------- All Image Types Settings ----------------------
    ;   KERNELFIXUPS = ON (sections to which the kernel can write are 
    ;                      relocated to the start of RAM)
    ;   SRE = ON (Romimage.exe produces an .sre file)
    ; ----------------------------------------------------------------------
        KERNELFIXUPS=ON
    
    ; --------------------------- RAM image --------------------------------
    ;   AUTOSIZE = ON (allows NK and RAM space to resize automatically)
    ;   ROMSIZE  = 0x04000000 (64 MB)
    ;   ROMSTART = 0x80200000 (SDRAM base + 2 MB offset for reserved region)
    ;   ROMWIDTH = 32 (32-bit wide memory, entire image in one file)
    ;
    ; Note:  Since we run the bootloader with MMU on, we do not need to
    ;        adjust virtual addresses back to physical.  If we need
    ;        to adjust to physical, the calculation would look something
    ;        like this:
    ;
    ;   ROMOFFSET = (SDRAM_PHYSICAL_START - ROMSTART) % 0x100000000
    ;             = (0x80000000 - 0x80000000) % 0x100000000 = 0x00000000
    ; ----------------------------------------------------------------------
    IF IMGFLASH !
        AUTOSIZE=ON
        ROMSTART=$(NK_START)
        ROMSIZE= $(NK_SIZE)
        ROMWIDTH=32
        IF IMGNAND
            ; ROMOFFSET = (FLASH_PHYSICAL_ADDRESS - ROMSTART) % 0x100000000
            ;           = (0x84200000 -  0x80200000) % 0x10000000 = 4200000
            ROMOFFSET=4200000
        ENDIF
        IF IMGSDMMC
            ; ROMOFFSET = (FLASH PHYSICAL ADDRESS - ULDR_PHSYICAL_START) % 0x100000000
            ;           = ( 0x87F00000            -  0x80200000      ) % 0x10000000 = 7D00000
            ROMOFFSET=7d00000
        ENDIF
    ENDIF
    
    ; ------------------- FLASH image with/without EBOOT -------------------
    ;   ROMSIZE  = 0x04000000 (64 MB)
    ;   ROMSTART = 0x90000000 (NOR virtual address base)
    ;   ROMWIDTH = 32 (32-bit wide memory, entire image in one file)
    ; ----------------------------------------------------------------------
    IF IMGFLASH
        IF IMGEBOOT
            ROMSIZE=03FC0000
            ROMSTART=90040000
        ENDIF
        IF IMGEBOOT !
            ROMSIZE=04000000
            ROMSTART=90000000
        ENDIF
        ROMWIDTH=32
    ENDIF
    
    ;;@CESYSGEN IF !NK_NKNOCOMP
    ;;COMPRESSION=ON
    ;;@CESYSGEN ENDIF !NK_NKNOCOMP
    ;;@CESYSGEN IF NK_NKNOCOMP
    ;;@CESYSGEN ENDIF NK_NKNOCOMP
    COMPRESSION=OFF
    ;DLLADDR_AUTOSIZE=ON
    
    ; --------------------- Profiling kernel support -----------------------
    ;   PROFILE = ON  (includes profiler structure and symbols in image)
    ;   PROFILE = OFF (does not include profiler structure and symbols)
    ; ----------------------------------------------------------------------
    IF IMGPROFILER
       PROFILE=ON
    ELSE
       PROFILE=OFF
    ENDIF
    
    FSRAMPERCENT=0x40404040
    
    ;
    ; ROMFLAGS is a bitmask of options for the kernel
    ;   ROMFLAGS    0x0001  Disallow Paging
    ;   ROMFLAGS    0x0002  Not all KMode
    ;   ROMFLAGS    0x0010  Trust Module only
    ;
    IF IMGTRUSTROMONLY
           ROMFLAGS=10
    ELSE
           ROMFLAGS=00
    ENDIF
    ; EOF config.bib
    
    and I have Bootloader sbproject in BSP tree(in Visual tudio)] with some code. So which file  I must use?

    Wednesday, July 11, 2012 6:46 AM
  • There isn't any file under C:\<WINCEROOT>\PLATFORM\<BSP>\SRC\INC  ?

    config.bib file is for memory configuration of NK, RAM, Bootloader and it is based on virtual memory addresses...you need OEMAddressTable.

    Wednesday, July 11, 2012 6:51 AM
  • for example I have

    ..\Bsp_Folder\scr\bootloader\common\loader.h

    //
    // Copyright (c) Microsoft Corporation.  All rights reserved.
    //
    //
    // Use of this source code is subject to the terms of the Microsoft end-user
    // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
    // If you did not accept the terms of the EULA, you are not authorized to use
    // this source code. For a copy of the EULA, please see the LICENSE.RTF on your
    // install media.
    //
    //-----------------------------------------------------------------------------
    //
    //  Copyright (C) 2007-2009, Freescale Semiconductor, Inc. All Rights Reserved.
    //  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
    //  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
    //
    //-----------------------------------------------------------------------------
    //
    //  File: loader.h
    //
    //  This file contains definitions specific to the bootloader.
    //
    //------------------------------------------------------------------------------
    #ifndef _LOADER_H_
    #define _LOADER_H_
    
    #pragma warning(push)
    #pragma warning(disable: 4201)
    #include <blcommon.h>
    #include <halether.h>
    #include <image_cfg.h>
    #include <oal_kitl.h>
    #include "menu.h"
    #pragma warning(pop)
    
    //------------------------------------------------------------------------------
    // Defines
    //
    #define EBOOT_VERSION_MAJOR                 1
    #define EBOOT_VERSION_MINOR                 0
    #define EBOOT_CFG_MAGIC_NUMBER              0x01020304
    
    #define SBOOT_VERSION_MAJOR                 1
    #define SBOOT_VERSION_MINOR                 0
    #define SBOOT_CFG_MAGIC_NUMBER              0x04030201
    
    #define BOOT_TOTAL_RAM_SIZE                0x200000  // see eboot.bib/sboot.bib to compute size
    #define BOOT_FLASHBLOCK_CACHE_START        ((UINT32) OALPAtoVA(IMAGE_BOOT_RAMDEV_RAM_PA_START, FALSE) + BOOT_TOTAL_RAM_SIZE)
    
    
    #define XLDR_NB0_FILE                       "xldr.nb0"
    #define XLDR_NB0_FILE_LEN                   8   // 8 chars in name
    #define EBOOT_NB0_FILE                      "eboot.nb0"
    #define EBOOT_NB0_FILE_LEN                  9   // 9 chars in name
    #define EBOOT_MSB_FILE                      "eboot.msb"
    #define EBOOT_MSB_FILE_LEN                  9   // 9 chars in name
    #define SBOOT_NB0_FILE                      "sboot.nb0"
    #define SBOOT_NB0_FILE_LEN                  9   // 9 chars in name
    #define NK_NB0_FILE                         "nk.nb0"
    #define NK_NB0_FILE_LEN                     6   // 6 chars in name
    #define NK_MSB_FILE                         "nk.msb"
    #define NK_MSB_FILE_LEN                     6   // 6 chars in name
    
    
    #define BOOT_CFG_AUTODOWNLOAD_NONE          0
    #define BOOT_CFG_AUTODOWNLOAD_NK_NOR        1
    #define BOOT_CFG_AUTODOWNLOAD_NK_NAND       2
    #define BOOT_CFG_AUTODOWNLOAD_IPL_NAND      3
    #define BOOT_CFG_AUTODOWNLOAD_NK_SD         4
    
    #define SBOOT_PARITY_EVEN                   0
    #define SBOOT_PARITY_ODD                    1
    #define SBOOT_PARITY_NONE                   2
    
    #define SBOOT_FLOWCTRL_OFF                  0
    #define SBOOT_FLOWCTRL_ON                   1
    
    #define SBOOT_DATABITS_7                    0
    #define SBOOT_DATABITS_8                    1
    
    #define SBOOT_STOPBITS_1                    0
    #define SBOOT_STOPBITS_2                    1
    
    #define BOOT_CFG_MODE_ETHERNET              0
    #define BOOT_CFG_MODE_SERIAL                1
    
    #define SBOOT_BAUDRATE_9600                 9600
    #define SBOOT_BAUDRATE_19200                19200
    #define SBOOT_BAUDRATE_38400                38400
    #define SBOOT_BAUDRATE_57600                57600
    #define SBOOT_BAUDRATE_115200               115200
    
    
    #define DEFAULT_SBOOT_CHANNEL               3
    #define DEFAULT_SBOOT_BAUDRATE              SBOOT_BAUDRATE_115200
    #define DEFAULT_SBOOT_BASE_REG              CSP_BASE_REG_PA_UART3
    
    #define FLASH_UUID_STR_SIZE                 (100 + 4)       // 'UUID' + Stored UUID string 
    #define UUID_SIZE                           4               // 'UUID' Block recognizing string
    
    //------------------------------------------------------------------------------
    // Structure definitions.
    //
    //------------------------------------------------------------------------------
    // Structure definitions.
    //
    // The BOOT_CFG structure holds a variety of configuration parameters.
    // When adding new parameters, make sure that the size of the structure in bytes is
    // an integral number of WORDS.  Pad the structure if necessary.
    // Add new members at the end. Also remember to increment the EBOOT version
    // numbers.
    #define EBOOT_CFG_MAGIC_NUMBER              0x01020304
    #define EBOOT_CFG_AUTODOWNLOAD_NONE         0
    #define EBOOT_CFG_AUTODOWNLOAD_NK_NOR       1
    #define EBOOT_CFG_AUTODOWNLOAD_NK_NAND      2
    #define EBOOT_CFG_AUTODOWNLOAD_IPL_NAND     3
    
    #define CONFIG_FLAGS_KITL_INT                   (1 << 0)
    #define CONFIG_FLAGS_KITL_PASSIVE               (1 << 1)
    #define CONFIG_FLAGS_USBKITL                    (1 << 2)
    
    #define SDBG_USB_SERIAL   101
    
    typedef struct
    {
        UINT32 recordOffset;
        UINT8  *pReadBuffer;
        UINT32 readSize;
    } BOOT_BINDIO_CONTEXT;
    
    //------------------------------------------------------------------------------
    // Enumerated type definitions.
    //
    
    typedef enum
    {
        IMAGE_TYPE_NK,
        IMAGE_TYPE_BOOT,
        IMAGE_TYPE_IPL,
        IMAGE_TYPE_BINDIO,
        IMAGE_TYPE_XLDR
    } IMAGE_TYPE, *PIMAGE_TYPE;
    
    typedef enum
    {
        IMAGE_MEMORY_RAM,
        IMAGE_MEMORY_NAND,
        IMAGE_MEMORY_NOR,
        IMAGE_MEMORY_SD
    } IMAGE_MEMORY, *PIMAGE_MEMORY;
    
    
    //------------------------------------------------------------------------------
    // External functions
    //
    extern void OEMBootInit();
    extern BOOL GetPreDownloadInfo(PBOOT_CFG p_bootCfg);
    extern void GetLaunchInfo(void);
    extern void SpinForever(void);
    extern void OEMRepeatDebugByte(UINT8 ch, UINT32 repeatCnt);
    extern DWORD OEMEthGetSecs(void);
    extern void BootTimerInit(void);
    extern UINT32 InitSpecifiedEthDevice(OAL_KITL_ARGS *pKITLArgs, UINT32 EthDevice);
    extern BOOL FlashLoadBootCFG(BYTE *pBootCfg, DWORD cbBootCfgSize);
    extern BOOL FlashStoreBootCFG(BYTE *pBootCfg, DWORD cbBootCfgSize);
    
    //#define IMAGE_BOOT_BOOTCFG_NAND_SIZE  FLASH_ARGS_LENGTH
    
    #define SGTL_FLASH_PHYS_BASE_ADDRESS    0//0x60000000
    #define SGTL_FLASH_SIZE                 0x4000000
    
    // BCB region:
    #define FLASH_BCB_ADDRESS               (SGTL_FLASH_PHYS_BASE_ADDRESS)
    #define FLASH_BCB_LENGTH                0x00300000
    
    // EBOOT Args region:
    #define FLASH_ARGS_ADDRESS              (FLASH_BCB_ADDRESS + FLASH_BCB_LENGTH)
    #define FLASH_ARGS_LENGTH               0x00040000
    
    // EBOOT region:
    #define FLASH_EBOOT_ADDRESS             (FLASH_ARGS_ADDRESS + FLASH_ARGS_LENGTH) 
    #define FLASH_EBOOT_LENGTH              0x00100000 
    
    // This should match address in FMD driver 0x3C0000
    #define FLASH_UUID_ADDRESS              (FLASH_EBOOT_ADDRESS + FLASH_EBOOT_LENGTH) 
    #define FLASH_UUID_SIZE                 0x00040000
    
    // BMP region:
    #define FLASH_BMP_IMAGE_ADDRESS         (FLASH_UUID_ADDRESS + FLASH_UUID_SIZE) 
    #define FLASH_BMP_IMAGE_SIZE            0x00080000 
    
    // Spare region:
    #define FLASH_EXTRA_SPACE               (FLASH_BMP_IMAGE_ADDRESS + FLASH_BMP_IMAGE_SIZE)
    #define FLASH_EXTRA_SPACE_LENGTH        0x00040000*8 // Leave 10 block 
    
    // OS (NK.BIN) region:
    #define FLASH_OS_ADDRESS                (FLASH_EXTRA_SPACE + FLASH_EXTRA_SPACE_LENGTH)
    #define FLASH_OS_LENGTH                 0x03000000
    
    
    
    
    // OEM reserved area bitfield.
    #define OEM_BLOCK_RESERVED              0x01
    #define OEM_BLOCK_READONLY              0x02
    
    #define NAND_SEARCH_STRIDE              64
    #define NAND_BB_SEARCH_NUMBER           20
    #define NAND0                           0
    
    #define NCB2_SECTOR_ADDRESS             (0*64)
    #define LDLB2_SECTOR_ADDRESS            (4*64)
    
    #define DBBT1_SECTOR_ADDRESS            (8*64)
    #define DBBT2_SECTOR_ADDRESS            (10*64)
    
    //for 64 secotr multiply by 2
    #define NCB2_BLOCK_ADDRESS              0
    #define LDLB2_BLOCK_ADDRESS             4
    
    #define DBBT1_BLOCK_ADDRESS             8
    #define DBBT2_BLOCK_ADDRESS             10
    
    
    #define FLASH_EBOOT_IMAGE_SIZE          0x80
    
    #define FLASH_EBOOT1_SECTOR_ADDRESS     (FLASH_EBOOT_ADDRESS / 2048 )
    #define FLASH_EBOOT2_SECTOR_ADDRESS     (FLASH_EBOOT1_SECTOR_ADDRESS + FLASH_EBOOT_IMAGE_SIZE)
    //#define FLASH_EBOOT2_SECTOR_ADDRESS   (FLASH_OS_ADDRESS + FLASH_OS_LENGTH) / 2048 )
    
    #define NAND_128_SECTOR_STRIDE          0x80
    
    //Bad blocks & DBBT related defines
    #define DBBT_DATA_START_PAGE_OFFSET     4
    #define BB_START_NO                     0x02
    #define BB_SECTOR_SEARCH_MARGIN         0x03
    // SectorsPerBlock(64) - beginning(3 Already searched) - end(Need to search 3) 
    #define BB_SECTOR_END_MARGIN            58 
    
    
    #define RAM_BUFFER_DBBT_2K_PAGE         0x40020000
    #define DBBT_MAX_2K_PAGES               (2048*10)
    
    // Chip information definations
    #define NAND_1K_PAGE                    1024
    #define NAND_2K_PAGE                    (NAND_1K_PAGE*2)
    #define NAND_4K_PAGE                    (NAND_1K_PAGE*4)
    
    #define NAND_64K_BLK                    (64*NAND_1K_PAGE)
    #define NAND_128K_BLK                   (128*NAND_1K_PAGE)
    #define NAND_256K_BLK                   (256*NAND_1K_PAGE)
    #define NAND_512K_BLK                   (512*NAND_1K_PAGE)
    
    #define NAND_64_SECTOR_BLK              64
    #define NAND_128_SECTOR_BLK             128
    #define NAND_256_SECTOR_BLK             256
    
    #define FLASH_SECTOR_BUFFER_SIZE        (NAND_1K_PAGE*4)
    #define FLASH_SECTOR_INFO_BUFFER_SIZE   256
    
    
    extern BOOLEAN g_SerialUSBDownload;
    extern BOOLEAN g_StorageSDDownload;
    
    
    #endif  // _LOADER_H_
    

    Wednesday, July 11, 2012 6:55 AM
  • Supposing that the BSP you're using the is  %_WINCEROOT%\PLATFORM\iMX233-EVK-PDK1_7 the OEM address table is in %_WINCEROOT%\PLATFORM\iMX233-EVK-PDK1_7\SRC\INC\oemaddrtab_cfg.inc:

    ALIGN
    g_oalAddressTable
        DCD 0x80000000, 0x40000000, 128         ; RAM image mapping
        DCD 0x88000000, 0x00000000, 1           ; On-chip RAM    
        DCD 0x90000000, 0x80000000, 1    
        DCD 0x90100000, 0x53A00000, 1           ; SPI NOR flash (= IMAGE_BOOT_BOOTIMAGE_NOR_PA_START)       
        DCD 0x00000000, 0x00000000, 0           ; Terminate table


    Luca Calligaris lucaDOTcalligarisATeurotechDOTcom www.eurotech.com Check my blog: http://lcalligaris.wordpress.com

    Wednesday, July 11, 2012 7:34 AM
  • You are providing us a lot of files but you have to search inside the following path for a .inc file :

     C:\<WINCEROOT>\PLATFORM\<BSP>\SRC\INC

    Tipicalli oemaddrtab_cfg.inc or addrtab_cfg.inc.

    Wednesday, July 11, 2012 7:46 AM
  • Yes. this is BSP for imx233, but I use version 1_8

    I must change only this one file or something else?

    I want change this BSP and run wince on my board.

    As I understand BSP created for freescale demoboard, but I use other board. So First of all I must change boot address for my nand flash.

    can you tell me how can I know what new address I must write? where I can found this info?

    I have datasheet for my flash.

    http://sdrv.ms/Nid7Xm

    Sorry for my newbie question, but I want start develop for embedded system, and hope for WinCe community help.


    • Edited by Artem Wednesday, July 11, 2012 8:35 AM
    Wednesday, July 11, 2012 8:33 AM
  • Hi Artem,

    I used IMX51 evk. Later moved custom board. I made changes in below files.

    C:\WINCE600\PLATFORM\COMMON\SRC\SOC\COMMON_FSL_V2_PDK1_7\NAND\INC\NANDTYPES.h
    C:\WINCE600\PLATFORM\COMMON\SRC\SOC\COMMON_FSL_V2_PDK1_7\NAND\INC\MT29F1G08.h  // I used Micron chip
    C:\WINCE600\PLATFORM\COMMON\SRC\SOC\COMMON_FSL_V2_PDK1_7\NAND\INC\MT29F1G08.inc  ; this is for xloader
    C:\WINCE600\PLATFORM\HSGW_IMX51_BSP\SRC\INC\oemaddrtab_cfg.inc

    oemaddrtab_cfg.inc

    ****************

    g_oalAddressTable

        IF :DEF: IMGRAM256
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 256           ; RAM image mapping
        ELSE   
        IF :DEF: IMGRAM128
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 128           ; RAM image mapping
        ELSE   
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 256           ; RAM image mapping
        DCD 0x90000000, CSP_BASE_MEM_PA_CSD1, 192           ; Remaining 64M are reserved for IPU
        ENDIF   
        ENDIF   
        DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping
        DCD 0x9F300000, CSP_BASE_MEM_PA_CS1, 1              ; WEIM CS1
        DCD 0x9F400000, CSP_BASE_MEM_PA_CS5, 1              ; WEIM CS5
        DCD 0x9F500000, CSP_BASE_MEM_PA_NFC_1MB, 5          ; NFC internal buffer
        IF :DEF: BSP_SI_VER_TO2
        DCD 0x9FA00000, CSP_BASE_MEM_PA_IRAM_1MB_TO2, 1     ; Internal RAM
        DCD 0x9FB00000, CSP_BASE_REG_PA_TZIC_TO2, 1         ; TZIC regs
        ELSE   
        DCD 0x9FA00000, CSP_BASE_MEM_PA_IRAM_1MB, 1         ; Internal RAM
        DCD 0x9FB00000, CSP_BASE_REG_PA_TZIC_1MB, 1         ; TZIC regs
        ENDIF   
        DCD 0x9FC00000, CSP_BASE_MEM_PA_ROM, 1              ; Internal ROM
        DCD 0x9FD00000, CSP_BASE_MEM_PA_AIPS1, 1            ; AIPS1 SPBA peripheral regs
        DCD 0x9FE00000, CSP_BASE_REG_PA_AIPS1, 1            ; AIPS1 peripheral regs
        DCD 0x9FF00000, CSP_BASE_REG_PA_AIPS2, 1            ; AIPS2 peripheral regs
        DCD 0x00000000, 0x00000000, 0                       ; Terminate table

    Regards,

    Kiran


    kiran reddy

    Wednesday, July 11, 2012 8:57 AM
  • MT29F1G08.h this is file for you flash chip? or you change existing file?

    As I understand I can create file k9f2g08u0c.h and k9f2g08u0c.inc and copy it to folder, and then change NANDTYPES.h?

    • Edited by Artem Wednesday, July 11, 2012 9:09 AM
    Wednesday, July 11, 2012 9:05 AM
  • MT29F1G08.h was not available with existing BSP. I modfiied MT29F32G08.h as per MT29F1G08 datasheet.

    kiran reddy

    Wednesday, July 11, 2012 9:10 AM
  • I modified to ))

    what you add to NANDTYPES.h

    my current file

    //
    // Copyright (c) Microsoft Corporation.  All rights reserved.
    //
    //
    // Use of this source code is subject to the terms of the Microsoft end-user
    // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
    // If you did not accept the terms of the EULA, you are not authorized to use
    // this source code. For a copy of the EULA, please see the LICENSE.RTF on your
    // install media.
    //
    //------------------------------------------------------------------------------
    //
    //  Copyright (C) 2007-2009, Freescale Semiconductor, Inc. All Rights Reserved.
    //  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
    //  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
    //
    //------------------------------------------------------------------------------
    //
    //  File:  NANDtypes.h
    //
    //  Contains definitions for FMD impletation of NAND flash memory device.
    //
    //------------------------------------------------------------------------------
    #ifndef __NAND_TYPES_H__
    #define __NAND_TYPES_H__
    
    NandChipInfo ChipInfo[] = 
    {
        //MT29F16G08
        {
            {NAND, 4096, 4096 * 128, 128, 4096},        //FlashInfo   fi; 
            {0x2C, 0xD5, 0x94, 0x3e},                   //BYTE        NANDCode[NANDID_LENGTH]
            3,                                          //BYTE        NumBlockCycles
            5,                                          //BYTE        ChipAddrCycleNum
            8,                                          //BYTE        DataWidth
            1,                                          //BYTE        BBMarkNum
            {0},                                        //BYTE        BBMarkPage
            6,                                          //BYTE        StatusBusyBit
            0,                                          //BYTE        StatusErrorBit
            218,                                        //WORD        SpareDataLength
            0x70,                                       //BYTE        CmdReadStatus
            0x00,                                       //BYTE        CmdRead1
            0x30,                                       //BYTE        CmdRead2
            0x90,                                       //BYTE        CmdReadId
            0xff,                                       //BYTE        CmdReset
            0x80,                                       //BYTE        CmdWrite1
            0x10,                                       //BYTE        CmdWrite2
            0x60,                                       //BYTE        CmdErase1
            0xD0,                                       //BYTE        CmdErase2
            {25, 16, 25, 20}                            //NANDTiming  timings
        },
        //MT29F8G08
        {
            {NAND, 4096, 2048 * 128, 128, 2048},        //FlashInfo   fi;     
            {0x2C, 0xD3, 0x94, 0x2d},                   //BYTE        NANDCode[NANDID_LENGTH]
            3,                                          //BYTE        NumBlockCycles
            5,                                          //BYTE        ChipAddrCycleNum
            8,                                          //BYTE        DataWidth
            1,                                          //BYTE        BBMarkNum
            {0},                                        //BYTE        BBMarkPage
            6,                                          //BYTE        StatusBusyBit
            0,                                          //BYTE        StatusErrorBit
            64,                                        //WORD        SpareDataLength
            0x70,                                       //BYTE        CmdReadStatus
            0x00,                                       //BYTE        CmdRead1
            0x30,                                       //BYTE        CmdRead2
            0x90,                                       //BYTE        CmdReadId
            0xff,                                       //BYTE        CmdReset
            0x80,                                       //BYTE        CmdWrite1
            0x10,                                       //BYTE        CmdWrite2
            0x60,                                       //BYTE        CmdErase1
            0xD0,                                       //BYTE        CmdErase2
            {25, 16, 25, 20}                             //NANDTiming  timings
        },
        //MT29F16G08DAA
        {
            {NAND, 4096, 4096 * 64, 64, 4096},        //FlashInfo   fi;     
            {0x2C, 0xD3, 0x90, 0x2e},                   //BYTE        NANDCode[NANDID_LENGTH]
            3,                                          //BYTE        NumBlockCycles
            5,                                          //BYTE        ChipAddrCycleNum
            8,                                          //BYTE        DataWidth
            1,                                          //BYTE        BBMarkNum
            {0},                                        //BYTE        BBMarkPage
            6,                                          //BYTE        StatusBusyBit
            0,                                          //BYTE        StatusErrorBit
            218,                                        //WORD        SpareDataLength
            0x70,                                       //BYTE        CmdReadStatus
            0x00,                                       //BYTE        CmdRead1
            0x30,                                       //BYTE        CmdRead2
            0x90,                                       //BYTE        CmdReadId
            0xff,                                       //BYTE        CmdReset
            0x80,                                       //BYTE        CmdWrite1
            0x10,                                       //BYTE        CmdWrite2
            0x60,                                       //BYTE        CmdErase1
            0xD0,                                       //BYTE        CmdErase2
            {11, 8, 15, 20}                             //NANDTiming  timings
        },
        //K9LBG08U0D
        {
            {NAND, 8192, 4096 * 128, 128, 4096},        //FlashInfo   fi;     
            {0xEC, 0xD7, 0xD5, 0x29},                   //BYTE        NANDCode[NANDID_LENGTH]
            3,                                          //BYTE        NumBlockCycles
            5,                                          //BYTE        ChipAddrCycleNum
            8,                                          //BYTE        DataWidth
            1,                                          //BYTE        BBMarkNum
            {127},                                      //BYTE        BBMarkPage
            6,                                          //BYTE        StatusBusyBit
            0,                                          //BYTE        StatusErrorBit
            218,                                        //WORD        SpareDataLength
            0x70,                                       //BYTE        CmdReadStatus
            0x00,                                       //BYTE        CmdRead1
            0x30,                                       //BYTE        CmdRead2
            0x90,                                       //BYTE        CmdReadId
            0xff,                                       //BYTE        CmdReset
            0x80,                                       //BYTE        CmdWrite1
            0x10,                                       //BYTE        CmdWrite2
            0x60,                                       //BYTE        CmdErase1
            0xD0,                                       //BYTE        CmdErase2
            {20, 8, 15, 20}                             //NANDTiming  timings
        },
    };
    
    #endif    // __NAND_TYPES_H__
    
    

    I must add info from my K9F2G08U0C.h?

    and what I must add to g_oalAddressTable for my chip?

    Wednesday, July 11, 2012 10:04 AM
  • Yes. Add new entry in ChipInfo.

    //K9F2G08U0C

    {

           //Fill data

    }

    in g_oalAddressTable add chipselect info and NFC internal buffer info.

    DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping
        DCD 0x9F300000, CSP_BASE_MEM_PA_CS1, 1              ; WEIM CS1
        DCD 0x9F400000, CSP_BASE_MEM_PA_CS5, 1              ; WEIM CS5
        DCD 0x9F500000, CSP_BASE_MEM_PA_NFC_1MB, 5          ; NFC internal buffer


    kiran reddy



    • Edited by SingamReddy Wednesday, July 11, 2012 10:15 AM
    Wednesday, July 11, 2012 10:13 AM
  • So i create this file

    K9F2G08U0C.h

    //
    // Copyright (c) Microsoft Corporation.  All rights reserved.
    //
    //
    // Use of this source code is subject to the terms of the Microsoft end-user
    // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
    // If you did not accept the terms of the EULA, you are not authorized to use
    // this source code. For a copy of the EULA, please see the LICENSE.RTF on your
    // install media.
    //
    //------------------------------------------------------------------------------
    //
    //  Copyright (C) 2007-2008, Freescale Semiconductor, Inc. All Rights Reserved.
    //  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
    //  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
    //
    //------------------------------------------------------------------------------
    //
    //  File:  MT29F32G08.h
    //
    //  Contains definitions for FMD impletation of the Micron MT29F32G08QAA NAND
    //  flash memory device.
    //
    //------------------------------------------------------------------------------
    #ifndef __K9F2G08U0C_H__
    #define __K9F2G08U0C_H__
    
    
    // NAND Flash Chip CMD
    #define CMD_READID              (0x90)      // Read ID
    #define CMD_READ                (0x00)      // Read data 1st cycle
    #define CMD_READ2               (0x30)      // Read data 2nd cycle
    #define CMD_RESET               (0xFF)      // Reset
    #define CMD_ERASE               (0x60)      // Erase setup
    #define CMD_ERASE2              (0xD0)      // Erase 
    #define CMD_WRITE               (0x80)      // Sequential data input
    #define CMD_WRITE2              (0x10)      // Program
    #define CMD_STATUS              (0x70)      // Read status
    
    // NAND Flash Chip Size
    #define NAND_BLOCK_CNT          (2048)      
    #define NAND_PAGE_CNT           (128)       
    #define NAND_PAGE_SIZE          (2048)      
    #define NAND_SPARE_SIZE         (64)        
    #define NAND_BUS_WIDTH          (8)         
    
    // NAND Flash Chip
    #define NAND_NUM_OF_CS          (1)
    
    // NAND Flash Chip ID
    #define NAND_MAKER_CODE         (0xEC)
    #define NAND_DEVICE_CODE        (0xD5)
    #define NAND_ID_CODE            ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)
    
    // NAND Flash Chip Operation Status
    #define NAND_STATUS_ERROR_BIT   (0)         // Status Bit0 indicates error
    #define NAND_STATUS_BUSY_BIT    (6)         // Status Bit6 indicates busy
    
    // SWAP BBI
    #define BBI_MAIN_ADDR           (464)       // Bad block info address offset    
    #define BBI_NUM                 (1)
    BYTE    BBMarkPage[1] = {127};
    
    #endif    // __K9F2G08U0C_H__
    
    

    K9F2G08U0C.inc

    ;------------------------------------------------------------------------------
    ;
    ;   Copyright (C) 2007-2009, Freescale Semiconductor, Inc. All Rights Reserved.
    ;   THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
    ;   AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
    ;
    ;------------------------------------------------------------------------------
    ;
    ;   File:  K9G8G08U0M.inc
    ;
    ;   Contains definitions for K9G8G08U0M NAND 
    ;   flash memory device.
    ;
    ;------------------------------------------------------------------------------
    
    CMD_READID              EQU     0x90        ; Read ID
    CMD_READ                EQU     0x00        ; Read data field
    CMD_READ2CYCLE          EQU     0x30        ; Read CMD second cycle
    CMD_READ2               EQU     0x50        ; Read spare field
    CMD_RESET               EQU     0xFF        ; Reset
    CMD_ERASE               EQU     0x60        ; Erase setup
    CMD_ERASE2              EQU     0xD0        ; Erase 
    CMD_WRITE               EQU     0x80        ; Sequential data input
    CMD_WRITE2              EQU     0x10        ; Program
    CMD_STATUS              EQU     0x70        ; Read status
    
    NAND_PAGE_CNT_LSH       EQU (7)         ; 2^7
    NAND_PAGE_SIZE_LSH      EQU (11)        ; 2^11  
    NAND_BLOCK_SIZE_LSH     EQU     (NAND_PAGE_CNT_LSH+NAND_PAGE_SIZE_LSH)        
    
    NAND_PAGE_CNT           EQU     (1 << NAND_PAGE_CNT_LSH)       
    NAND_PAGE_SIZE          EQU     (1 << NAND_PAGE_SIZE_LSH)      
    NAND_BLOCK_SIZE         EQU     (1 << NAND_BLOCK_SIZE_LSH)
    NAND_BLOCK_CNT          EQU     (2048) 
    NAND_SPARE_SIZE         EQU     (64) 
    
    BBI_PAGE_NUM            EQU     (1)                         ;NAND flash bad block information(BBI) page numbers
    BBI_PAGE_ADDR_1         EQU     (NAND_PAGE_CNT - 1)     ;NAND flash bbi page address
    BBI_PAGE_ADDR_2         EQU     (NAND_PAGE_CNT - 1)     ;NAND flash bbi page address
    
    NUM_OF_NAND_DEVICES     EQU     1           ;  Number of NAND device
    NUM_OF_NAND_DEVICES_LSH EQU     0           ;       
    
    NAND_BUS_WIDTH          EQU     8           ; 8-bit bus
    
        END
    


    and add to NANDTYPES.h this

    //K9F2G08U0C
    	{
    		{NAND, 2048, 2048 * 128, 128, 2048},        //FlashInfo   fi;     
            {0xEC, 0xD7, 0xD5, 0x29},                   //BYTE        NANDCode[NANDID_LENGTH]
            3,                                          //BYTE        NumBlockCycles
            5,                                          //BYTE        ChipAddrCycleNum
            8,                                          //BYTE        DataWidth
            1,                                          //BYTE        BBMarkNum
            {127},                                      //BYTE        BBMarkPage
            6,                                          //BYTE        StatusBusyBit
            0,                                          //BYTE        StatusErrorBit
            218,                                        //WORD        SpareDataLength
            0x70,                                       //BYTE        CmdReadStatus
            0x00,                                       //BYTE        CmdRead1
            0x30,                                       //BYTE        CmdRead2
            0x90,                                       //BYTE        CmdReadId
            0xff,                                       //BYTE        CmdReset
            0x80,                                       //BYTE        CmdWrite1
            0x10,                                       //BYTE        CmdWrite2
            0x60,                                       //BYTE        CmdErase1
            0xD0,                                       //BYTE        CmdErase2
            {20, 8, 15, 20} 
    	}

    oemaddrtab_cfg.inc

    DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 256           ; RAM image mapping
    	DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping
        DCD 0x9F300000, CSP_BASE_MEM_PA_CS1, 1              ; WEIM CS1
        DCD 0x9F400000, CSP_BASE_MEM_PA_CS5, 1              ; WEIM CS5
        DCD 0x9F500000, CSP_BASE_MEM_PA_NFC_1MB, 5
    	DCD 0x9FC00000, CSP_BASE_MEM_PA_ROM, 1              ; Internal ROM
        DCD 0x9FD00000, CSP_BASE_MEM_PA_AIPS1, 1            ; AIPS1 SPBA peripheral regs
        DCD 0x9FE00000, CSP_BASE_REG_PA_AIPS1, 1            ; AIPS1 peripheral regs
        DCD 0x9FF00000, CSP_BASE_REG_PA_AIPS2, 1            ; AIPS2 peripheral regs
    	DCD 0x00000000, 0x00000000, 0           ; Terminate table

    This files correct for my flash chip?

    Wednesday, July 11, 2012 11:33 AM
  • Please verify them using your chip data sheet.

    kiran reddy

    Thursday, July 12, 2012 2:42 AM
  • Thanks.

    And for NAND flash and bootloader no need change anything else?

    Can you tell me which file I must modify in BSP for RAM?

    Current BSP for 2x64Mb RAM

    My board have one 64Mb RAM.

    Where I can found files with RAM settings.

    Thanks and hope for you help.

    Thursday, July 12, 2012 7:49 AM
  • Hi,

    No chnages requierd. Bootloader refers the files which I mentioned already.

    oemaddrtab_cfg.inc and config.bib files need to be modified for RAM settings.

    For example

    g_oalAddressTable

        IF :DEF: IMGRAM256
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 256           ; RAM image mapping
        ELSE   
        IF :DEF: IMGRAM128
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 128           ; RAM image mapping
        ELSE   
        DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 256           ; RAM image mapping
        DCD 0x90000000, CSP_BASE_MEM_PA_CSD1, 192           ; Remaining 64M are reserved for IPU
        ENDIF   


    kiran reddy

    Thursday, July 12, 2012 8:14 AM
  • So for 64 mb ram my oemaddrtab_cfg.inc must be

    DCD 0x80000000, CSP_BASE_MEM_PA_CSD0, 64           ; RAM image mapping
    DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping
    DCD 0x9F300000, CSP_BASE_MEM_PA_CS1, 1              ; WEIM CS1
    DCD 0x9F400000, CSP_BASE_MEM_PA_CS5, 1              ; WEIM CS5
    DCD 0x9F500000, CSP_BASE_MEM_PA_NFC_1MB, 5
    DCD 0x9FC00000, CSP_BASE_MEM_PA_ROM, 1              ; Internal ROM
    DCD 0x9FD00000, CSP_BASE_MEM_PA_AIPS1, 1            ; AIPS1 SPBA peripheral regs
    DCD 0x9FE00000, CSP_BASE_REG_PA_AIPS1, 1            ; AIPS1 peripheral regs
    DCD 0x9FF00000, CSP_BASE_REG_PA_AIPS2, 1            ; AIPS2 peripheral regs
    DCD 0x00000000, 0x00000000, 0           ; Terminate table

    but I can't understand what mean

    DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping

    and for

    DCD 0x9F500000, CSP_BASE_MEM_PA_NFC_1MB, 5
    DCD 0x9FC00000, CSP_BASE_MEM_PA_ROM, 1              ; Internal ROM
    DCD 0x9FD00000, CSP_BASE_MEM_PA_AIPS1, 1            ; AIPS1 SPBA peripheral regs
    DCD 0x9FE00000, CSP_BASE_REG_PA_AIPS1, 1            ; AIPS1 peripheral regs
    DCD 0x9FF00000, CSP_BASE_REG_PA_AIPS2, 1            ; AIPS2 peripheral regs

    I must change addresses(like 0x9F500000) or not?

    Thursday, July 12, 2012 9:46 AM
  • DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping

    For chip select0 32 MB of Flash connected (It can be Nand/Nor/.....)

    Yes. Depending on your physical addresses mapping logical address changes.

    DCD 0x9D000000, CSP_BASE_MEM_PA_CS0, 32             ; FLASH image mapping

    kiran reddy

    Thursday, July 12, 2012 11:52 AM
  • where I can get info about oemaddrtab_cfg

    How Can I know what address I must set and what size for this.

    Thursday, July 12, 2012 12:32 PM
  • You need to look at the board schematics or, better, ask to the HW engineer who designed or modified it


    Luca Calligaris lucaDOTcalligarisATeurotechDOTcom www.eurotech.com Check my blog: http://lcalligaris.wordpress.com

    Thursday, July 12, 2012 12:50 PM
  • You have to look in to your schematics. Make sure that CS0 connected to FLASH. If not configure that particular CS physical address in the oem address table. For size refer your nand chip data sheet.

    kiran reddy

    Thursday, July 12, 2012 2:38 PM
  • I have change all files and build image. Now I try upload image to device. I try upload end load bootloader. But nothing work. I'm try load eboot.sb(use sb_loader.exe /f eboot.sb) but sb_loader return error -13. when I download eboot.bin or nk.bin sb_loader show download progress, but nothing happens after download finish. So I think this is because I do something wrong. Or I write incorrect memory addresses. Can you say something about this?

    Thanks and hope for you help.

    Sunday, July 15, 2012 12:23 PM