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USB Isochronous URB returns with less than expected transfer size in Intel xHCI Host controller. RRS feed

  • Question

  • Hello There,

    We are facing very weird problem in dealing with SS Isochronous transaction using Intel xHCI host controller.

    Mult - 2 (2+1), Burst - 14 (14+1) and Microframe size is 46080 (45K).

    We have a custom KMDF windows driver and an application. In the driver, URB's are created to return after 8 Millisecond of Isoch data capture (Size 0x2D0000 Bytes). And, several similar URB's are pending in the USBD stack for the device to send data.

    Now, I have connect LeCroy USB Analyzer to make sure all our indexed SS Isoch data are delivered to the Host Controller.

    With Intel xHCI controller:

    Some URB's return with lesser than expected transfer size (eg. < 0x2D0000 Bytes) and they are lesser by a 1/2 micro frame to 2 micro frame size. The USB traces cleanly shows that Host Controller has received all our indexed test data.

    I couldn't understand why Intel SS driver stack or Microsoft SS Host Controller driver stack lost the data. (This issue occurs both in Windows 8.1 and Windows 7)

    However, if burst the size is reduced to 12 (12+1), things started to work without any issue.

    With Fresco logic Host controller:

    The same driver and the application runs perfectly fine with a burst size of (14+1).

    Question:

    1.) Is there any known issue with Intel xHCI controller running SS Isoch transaction close to max USB 3.0 bandwidth?

    To me, it is pretty clear that Intel hardware Host Controller is messing up the SS data that's close to max. bandwidth. Can anyone point me to any errata that Intel put out talking about such defects?

    2.) We are confused to choose an acceptable Isoch bandwidth that works across all Host Controller. Any Pointers here will be very helpful.

    Thanks,

    Jegan

    Friday, November 14, 2014 1:17 PM

Answers

  • I agree that from your description, it does look like it could be a limitation of Intel host controller hardware. We are not aware of any errata issued by Intel related to this issue though. Of course, it is not a very common scenario; so it is quite likely that it just hasn't been discovered so far. You will need to follow up with Intel on this issue. By any chance, is the link going to U1/U2 at all as that can potentially impact bandwidth? If so, you can try to disable it by this tool: http://msdn.microsoft.com/en-us/library/windows/hardware/dn376879(v=vs.85).aspx and see if it makes a difference.

    Thanks,

    Vivek

    Monday, November 17, 2014 1:43 AM

All replies

  • I presume you are using Intel's driver stack on Windows 7, since Microsoft has not released a XHCI driver for Windows 7. For windows 8, are you using Microsoft driver stack? If not try with that if you see any difference.

    If you have access to a different XHCI hardware try on that. THat might give you insights on whether it is issue specific to a particular hardware.


    pg - This posting is provided "AS IS" with no warranties, and confers no rights.

    Saturday, November 15, 2014 2:53 AM
  • I agree that from your description, it does look like it could be a limitation of Intel host controller hardware. We are not aware of any errata issued by Intel related to this issue though. Of course, it is not a very common scenario; so it is quite likely that it just hasn't been discovered so far. You will need to follow up with Intel on this issue. By any chance, is the link going to U1/U2 at all as that can potentially impact bandwidth? If so, you can try to disable it by this tool: http://msdn.microsoft.com/en-us/library/windows/hardware/dn376879(v=vs.85).aspx and see if it makes a difference.

    Thanks,

    Vivek

    Monday, November 17, 2014 1:43 AM
  • Thanks Vivek for your inputs.

    In the device, we have disabled the LPM functionality during this testing. So, there is absolutely no chance of device accepting an enter to U1 or U2 mode. Device will always stay in U0 or operational mode.

    I have launched a technical support case with Intel to know about any errata in the xHCI Host Controller.

    Cheers,

    Jegan

    Tuesday, November 18, 2014 8:43 AM