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about dwTTBRCacheBits & dwPageTableCacheBits RRS feed

  • Question

  • Hi,

    Is there any publicly available info about format of these two variables? Google mostly gives links to MSDN which says nothing about their format eg for example how to set up TEX, C and B bits?

    Thanks

    • Edited by Jker Monday, November 14, 2011 9:16 AM
    Monday, November 14, 2011 9:13 AM

Answers

  • Please refer to Second-level descriptors in B3.3.1 Translation table entry formats of ARM manual (https://silver.arm.com/download/download.tm?pv=1164925, may need free registration for download)
    While TEX[2:0] is at bit 6 to 8 for PTE and C,B are bits 3 and 2.
    So the 0x140 means TEX = 0b101 CB = 00, therefor your AA (CB) = 00, BB (TEX[1:0])= 01, that is outer WAWB, inner non-cacheable.
    Actually, if you want to enhance the performance a little, you can set dwPageTableCacheBits  as 0x148.
    Although the HW PTE does not support from innter (L1) cache but by enabling innter WriteThrough can still burst the performance when software (kernel) accessing it during page fault.

    • Marked as answer by Jker Thursday, November 17, 2011 1:55 PM
    Monday, November 14, 2011 6:48 PM

All replies

  • This stuff is specific to ARM architecture and if you take a look at the ARM11 Technical Reference Manual, you can find the description of the relevant registers and the bits. As an example:

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344h/Bgbfdjaa.html

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211k/Babifihd.html

    See %_WINCEROOT%\private\winceos\COREOS\nk\kernel\arm\mdarm.c to check how dwTTBRCacheBits and dwPageTableCacheBits are used.

    By the way, MSDN documentation (http://msdn.microsoft.com/en-us/library/gg155702.aspx , http://msdn.microsoft.com/en-us/library/gg156114.aspx) states that you can find an example of how to set those variables in %_WINCEROOT%\Platform\imx313ds\src\oal\oallib\init.c:

        //----------------------------------------------------------------------
        // Make Page Tables walk L2 cacheable. There are 2 new fields in OEMGLOBAL
        // that we need to update:
        // dwTTBRCacheBits - the bits to set for TTBR to change page table walk
        //                   to be L2 cacheable. (ARM1136 TRM, section 3.2.31)
        //                   Set this to be "Outer Write-Back, Write-Allocate".
        // dwPageTableCacheBits - bits to indicate cacheability to access Level
        //                   L2 page table. We need to set it to "inner no cache,
        //                   outer write-back, write-allocate. i.e.
        //                      TEX = 0b101, and C=B=0.
        //                   (ARM1136 TRM, section 6.11.2, figure 6.7, small (4k) page)
        //----------------------------------------------------------------------
        g_pOemGlobal->dwTTBRCacheBits = 0x8;            // TTBR RGN set to 0b01 - outer write back, write-allocate
        g_pOemGlobal->dwPageTableCacheBits = 0x140;     // Page table cacheability uses 1BB/AA format, where AA = 0b00 (inner non-cached)
                                                        //BB = 0b01 (outer write back, write-allocate)
    
    


     


    Luca Calligaris lucaDOTcalligarisATeurotechDOTcom www.eurotech.com Check my blog: http://lcalligaris.wordpress.com
    Monday, November 14, 2011 10:58 AM
  • I am getting confused here.

    If 140 (hex) is 101000000 (bin) then what is 1BB/AA format?

    How did they get 101000000?

    According to them TEX = 0b101

    AA = 0b00

    BB = 0b01

    From ARM website:

    • the bits marked AA (C bit, B bit) are the inner cache policy bits

    • the bits marked BB (TEX[1:0] bits) are the outer cache policy bits.

    How to get 101000000 from these parameters?

    Why not 10100?

    I am lost.


    I have no acces to the private part. Any info from mdarm.c will be helpful.
    • Edited by Jker Monday, November 14, 2011 2:07 PM
    Monday, November 14, 2011 1:35 PM
  • Please refer to Second-level descriptors in B3.3.1 Translation table entry formats of ARM manual (https://silver.arm.com/download/download.tm?pv=1164925, may need free registration for download)
    While TEX[2:0] is at bit 6 to 8 for PTE and C,B are bits 3 and 2.
    So the 0x140 means TEX = 0b101 CB = 00, therefor your AA (CB) = 00, BB (TEX[1:0])= 01, that is outer WAWB, inner non-cacheable.
    Actually, if you want to enhance the performance a little, you can set dwPageTableCacheBits  as 0x148.
    Although the HW PTE does not support from innter (L1) cache but by enabling innter WriteThrough can still burst the performance when software (kernel) accessing it during page fault.

    • Marked as answer by Jker Thursday, November 17, 2011 1:55 PM
    Monday, November 14, 2011 6:48 PM