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PCIe Device that request 256 GB of memory for its BAR RRS feed

  • Question

  • Hi 

    We have a PCIe device that requests 256 GB of memory for its BAR[0].

    (using windows 7 x64 now and planning to use Win 10 x64 in the future)

    When device requests something small, like 1 MB for BAR 0, everything works fine,

    but  when the request grows to 1GB ,  we receive failure report on driver loading -> "not sufficient resources..."

    Is there some limit configuration in Windows for maximum memory resources that can be allocated by PCIe Device ?

    If so, how it can be changed ?

    thanks ahead

    regards

    Uri.

    Sunday, May 22, 2016 11:15 AM

Answers

  • Since you apparently have control over the amount requested, why would a device need a quarter terabyte of memory-mapped register space? If you'd ask the CPU to read it all, it would take hours to do that, since memory-mapped IO reads on PCIe take about 0.5 microseconds per word.

    My guess is that you confuse the "master" and "slave" modes. The BAR can access all PC memory in master mode if it wants to, even if the "slave" move size is set to say 4k or so.

    Monday, May 23, 2016 6:55 AM

All replies

  • Do you have access to the platform vendor, in case if BIOS change is needed?

    -- pa

    Sunday, May 22, 2016 12:39 PM
  • Since you apparently have control over the amount requested, why would a device need a quarter terabyte of memory-mapped register space? If you'd ask the CPU to read it all, it would take hours to do that, since memory-mapped IO reads on PCIe take about 0.5 microseconds per word.

    My guess is that you confuse the "master" and "slave" modes. The BAR can access all PC memory in master mode if it wants to, even if the "slave" move size is set to say 4k or so.

    Monday, May 23, 2016 6:55 AM
  • Hi

    Thanks for answering.

    No there is no confusion here .... :)

    The scenario that need to be supported  is as follows:

    Some standard Device "A" need to access Device "B" ("B" is our device with 256GB BAR)

    The access done by DMA on Device A . Both Devices connected to same PCIe switch, so all the transaction closed within the switch management (peer to peer) and CPU do not involved in this at all. 

    The FPGA on Device B will handle the access and answer to device A

    In order that our algorithms can cover all the cases, the Device A should be able to "see" 256GB of  address range on device B and generate requests to this range.

    Hope  i  managed to explain it clearly ... :)

    Uri.

    Thursday, May 26, 2016 7:54 AM
  • Hi

    No, It should be able to work on different motherboard with different BIOS vendors.

    in parallel to this thread question i'm also checking the possibility that it may be blocked by BIOS or  "chip set" on motherboard. 

    any way i would like to understand if  pcie bus driver or some other Windows mechanism has restrictions on BAR size.

    Thursday, May 26, 2016 8:00 AM