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Spi configuration not set as set it RRS feed

  • Question

  • Hi,

    I use OMAP3530 + Windows EC7 for our development.  I am trying to communicate with an external device from AM\DM37x application processor over SPI driver.  Actually I set the configuration as,

        config =    MCSPI_PHA_ODD_EDGES |
                    MCSPI_POL_ACTIVEHIGH |
                    MCSPI_CHCONF_CLKD(32) |
                    MCSPI_CSPOLARITY_ACTIVELOW |
                    MCSPI_CHCONF_WL(8) |
                    MCSPI_CHCONF_TRM_TXRX |
                    MCSPI_CHCONF_DMAW_DISABLE |
                    MCSPI_CHCONF_DMAR_DISABLE |
                    MCSPI_CHCONF_DPE0;

    but while debugging the code, I see the value as 0x103C0 that means clock divider haven't set accordingly.  On bits 2 to 5 should be 0x5, but I see only 0.  But other values are set as per the configuration I did.

    Can you please let know what could be the reason it is not set.

    Also, what could be the exact clock if I dive the SPI reference clock by 32.

    Regards,

    Karthick

    Thursday, September 3, 2015 1:15 PM

Answers

  • Hi Karthick,

    You have to refer the AM\DM37XX TRM manual for the SPI Clock information.

    If you are seeing CLOCK Divider different from what you are configuring, below might be possibilities

    1. What are the range of values allowed for it. (If you program a value with more than MAX allowed value you might see zero)
    2. The CLock divider value might be changing some where in the source code

    Best Regards,

    GSR

    • Marked as answer by Karthickph Friday, September 4, 2015 6:36 AM
    Friday, September 4, 2015 5:34 AM

All replies

  • Hi Karthick,

    You have to refer the AM\DM37XX TRM manual for the SPI Clock information.

    If you are seeing CLOCK Divider different from what you are configuring, below might be possibilities

    1. What are the range of values allowed for it. (If you program a value with more than MAX allowed value you might see zero)
    2. The CLock divider value might be changing some where in the source code

    Best Regards,

    GSR

    • Marked as answer by Karthickph Friday, September 4, 2015 6:36 AM
    Friday, September 4, 2015 5:34 AM
  • Thanks for the support.

    I had seen the AM37x TRM and for spi there was 48MHZ_FCLK derived.

    But I don't why in the spi configuration register there was soo many diver values (1 to 32768) were there.

    Also, from while debugging the spi driver I see the following msgs.

    82475 PID:400002 TID:1c9000a TRF_Init(): context Drivers\Active\48

     282475 PID:400002 TID:1c9000a +SPI_Open(0xcca18000, 0xc0000000, 0x00000003

     282476 PID:400002 TID:1c9000a -SPI_Open(rc = 0xcfc49aa0)

     282476 PID:400002 TID:1c9000a +SPI_IOControl(0xcfc49aa0, 0x00220400, 0xee531288, 16, 0xcfc49b80, 48, 0xcc40f578)

     282476 PID:400002 TID:1c9000a -SPI_IOControl(rc = 1)

     282477 PID:400002 TID:1c9000a SPI_Configure Addr = 0x1  Config = 0x103c0

     282477 PID:400002 TID:1c9000a SPI_config(0x000103c0)

     282478 PID:400002 TID:1c9000a +SPI_Write(0xcfc49aa0, 0xcc40f8d0, 0x00000001)

     282478 PID:400002 TID:1c9000a word_len(0x00000008)

     282478 PID:400002 TID:1c9000a SPI_TX_data(0x00000003)

    the code which I use as follows;

    #define SPI2_DEVICE_NAME         L"SPI2:"

        hSPI = SPIOpen(SPI2_DEVICE_NAME);

    config = MCSPI_PHA_ODD_EDGES |
    MCSPI_POL_ACTIVEHIGH |
    MCSPI_CHCONF_CLKD(2) |
    MCSPI_CSPOLARITY_ACTIVELOW |
    MCSPI_CHCONF_WL(8) |
    MCSPI_CHCONF_TRM_TXRX |
    MCSPI_CHCONF_DMAW_DISABLE |
    MCSPI_CHCONF_DMAR_DISABLE |
    MCSPI_CHCONF_DPE0;

    SPIConfigure(hSPI, 1, config);

    SPIWrite(hSPI, 1, 0x09);

    I don't know why Clean up function called when invoking SPI_Open and it's printing -SPI_Open(rc = 0xcfc49aa0)....

    Looks like due to which the spi driver can't write the value into MOSI line.  Please share your thoughts on what could be the reason it failed. (by analysing the DEBUG msgs)

    Friday, September 4, 2015 6:21 AM
  • Yes, you are right, while setting with MCSPI_CHCONF_CLKD(2) value the spi configuration is set accordingly.

    All works fine now, while SPIOpen() no errors were reported like incorrect context or failed to allocate a spi instance structure.  And the flow of the code is good and it reached by default to the Cleanup function and while exiting with -SPI_Open(rc = 0xcfc49aa0).

    Looks like the problem in the sequence (may be timing issue or clock issue) which I should follow to communicate with the device.

    Regards,
    Karthick

    Friday, September 4, 2015 8:39 AM
  • Hi Karthick,

    If SPI_Open is failing usually those stream driver entry function will return NULL on failure.

    In case you are seeing a valid context being returned by the SPI_Opne. If nothing is happening on SPI Lines you have to double check your SPI configurations in the Driver.

    Best Regards,

    GSR

    Saturday, September 5, 2015 6:43 AM
  • Thanks GSR.

    I see the valid context is done on SPI_Open.

    I did configuration for 6MHz clock generation on DAT_CLK line.

    But, I don't see the any clock generated on DATA clock line on write.  I verified the external device being communicated through SPI for power up and other setup.  It seems to be okay (I checked all h/w lines).

    the Spi driver configuration looks like;

        hSPI = SPIOpen(SPI2_DEVICE_NAME);

        config =    MCSPI_PHA_ODD_EDGES |
                    MCSPI_POL_ACTIVEHIGH |
                    MCSPI_CHCONF_CLKD(8) |
                    MCSPI_CSPOLARITY_ACTIVELOW |
                    MCSPI_CHCONF_WL(8) |
                    MCSPI_CHCONF_TRM_TXRX |
                    MCSPI_CHCONF_DMAW_DISABLE |
                    MCSPI_CHCONF_DMAR_DISABLE |
                    MCSPI_CHCONF_DPE0;

    SPIConfigure(hSPI, nSPIAddr, config);

    I don't know why the data clock generated on write operation.  Am I missing any configuration setttings. Can I know when the slave select (external device) is asserted in the function.

    Regards,

    Karthick

    Saturday, September 5, 2015 1:45 PM