Windows CE 6.0 R3 L2 Cache on iMX31 RRS feed

  • Question

  • I am trying to use on our LogicPD iMX31 based product. This iMX31 contains a MCMIMX31VKN5C processor and contains 128K of L2 cache. After installing the QFE and adding 'g_pOemGlobal->dwTTBRCacheBits = 0x08;' to my OEMInit() my kernel crashes with the following dump:

    OEM Initialization Done.
    Error Reporting Memory Reserved, dump size = 00040000
    Booting Windows CE version 6.00 for (ARM)
    CAMSMITHS - OEMCalcFSPages set to 16 . Total available pages = 21539
    Configuring: Primary pages: 21539, Secondary pages: 0, Filesystem pages = 16

    Booting kernel with clean memory configuration:
    Memory Sections:
    [0] : start: 8a292000, extension: 0000b000, length: 05423000

    Faulted in KCall, pCurThread->dwStartAddr = 00000000, PageFreeCount = 0000540a!!
    Original Context when thread faulted:
    Exception 'Data Abort'(4) Thread-Id=00410002(pth=8f6bf024) PC=00000000 BVA=d001fef8, dwInfo = 00000807
     R0=00000000  R1=00000000  R2=00000000  R3=00000000
     R4=00000000  R5=00000000  R6=00000000  R7=00000000
     R8=00000000  R9=00000000 R10=00000000 R11=00000000
    R12=00000000  SP=00000000  Lr=00000000 Psr=00000000
    Context when faulted in KCall:
    Exception 'Data Abort'(4) Thread-Id=00410002(pth=ffffc60c) PC=88224738 BVA=d001fef8, dwInfo = 00000807
     R0=d0010000  R1=8a28a308  R2=d0020000  R3=d001f000
     R4=d0010000  R5=00010000  R6=d0010000  R7=d001ff00
     R8=8a28a010  R9=d001ff00 R10=00000000 R11=8a28a308
    R12=00410003  SP=ffffc75c  Lr=88224684 Psr=60000013

    After reading through Freescales and ARMs TRM and RM it seems like my setting for 'dwTTBRCacheBits' is correct. The QFE is a little ambiguous so I am wondering if I am missing something. Our objective is to squeeze as much perofmance out of this platform as possible. All benchmarks we have run with L2 cache enabled or disabled show no difference in performance at all so it seems the L2 cache on this board is not being used by WEC6 R3.

    Thank you,



    There is an errata for the L2 cache controller in this core which advises not to use WRITE-BACK mode but rather use WRITE-THROUGH. The BSP's

    'OEMARMCacheMode' function contained in 'cachemode.s' should be modified to look like this:

            LEAF_ENTRY OEMARMCacheMode

            ; Set write back mode. *Original CODE

            ;mov r0, #0x0C

            ; Set write through mode. *New CODE

            mov   r0, #0x00000008



    This stops the kernel from crashing when using the above QFE and setting  'g_pOemGlobal->dwTTBRCacheBits = 0x08;'.

    I'll post performance delta's for this system in the future.

    Thank you,


    • Edited by S.Bosse Friday, September 7, 2012 8:28 AM Step Forward
    Thursday, August 30, 2012 3:43 PM